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Discussion :: Digital Electronics

  1. In a positive-edge-triggered JK flip-flop, a low J and a low K produce __________ state. A high __________ on the rising edge of the clock.

    2. A.
    inactive, reset
    B.
    active, reset
    C.
    active, toggle
    D.
    inactive, toggle

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    Answer : Option D

    Explanation :

    No answer description available for this question.

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