Home / ECE / Network Analysis and Synthesis :: Section 17

ECE :: Network Analysis and Synthesis

  1. Poor power factor

  2. A.
    reduces load handling capability of electrical system
    B.
    results in more power losses in the electrical system
    C.
    overloads alternators, transformers and distribution lines
    D.
    all

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  3. The input resistance of the network in figure is

  4. A.
    1.5 R
    B.
    C.
    D.

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  5. If two networks are cascaded then

  6. A.
    [y] = [ya] . [yb]
    B.
    [Z] = [Za] . [Zb]
    C.
    [aa] = [bb]
    D.
    [aa] + [bb]

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  7. When a series RL circuit is switched on to a dc voltage, the rate of change of current is maximum at t = 0.

  8. A.
    True
    B.
    False

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  9. In the set of equation

    x1 =

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  11. Z-matrix for the network shown in the given figure is

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  13. In a circuit containing a complex impedance, maximum power transfer takes place when load is

  14. A.
    pure resistance
    B.
    equal to the complex impedance
    C.
    conjugate complex of the circuit impedance
    D.
    none of the above

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  15. The resistance of a bulb at the time of full brightness is 1200 Ω. Then the resistance at room temperature is about

  16. A.
    1200 Ω
    B.
    120 Ω
    C.
    600 Ω
    D.
    10 Ω

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  17. For a delayed half wave rectified wave, the average and rms values are lower than those for half wave.

  18. A.
    True
    B.
    False

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  19. A reactance function is always a quotient of

  20. A.
    even to odd polynomials
    B.
    odd to even polynomials
    C.
    even to odd or odd to even polynomials
    D.
    even to even polynomials

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