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ECE :: Exam Questions Paper

  1. A 3 x 8 decoder with two enable inputs is to be used to address 8 blocks of memory. What will be the size of each memory block when addressed from a sixteen bit bus with two MSBs used to enable the decoder?

  2. A.
    2 K
    B.
    4 K
    C.
    16 K
    D.
    64 K

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  3. What is the purpose of a start in RS232 serial communication protocol?

  4. A.
    To synchronise receiver for receiving every byte
    B.
    To synchronise receiver for receiving a sequence of byte
    C.
    Acts as a parity bit
    D.
    To synchronise receiver for receiving the last byte

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  5. Time delay produced by an instruction code given below using 2 MHz clock is:
    MVI A, FFH
    LOOP: DCR A
    JNZ Loop

  6. A.
    1783 μs
    B.
    1787 μs
    C.
    1781 μs
    D.
    1797 μs

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  7. Refer to the NAND and NOR latches shown in the figure. The inputs (P1, P2) for both the latches are first made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs (Q1, Q2) are

  8. A.
    NAND: first (0, 1) then (0, 1) NOR: first (1, 0) then (0, 0)
    B.
    NAND: first (1, 0) then (1, 0) NOR: first (1, 0) then (1, 0)
    C.
    NAND: first (1, 0) then (1, 0) NOR: first (1, 0) then (0, 0)
    D.
    NAND: first (1, 0) then (1, 1) NOR: first (0, 1) then (0, 1)

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  9. Consider the following two statements about the internal conditions in an n-channel MOSFET operating in the active region
    S1: The inversion charge decreases from source to drain
    S2: The channel potential increases from source to drain
    Which of the following is correct?

  10. A.
    Only S2 is true
    B.
    Both S1 and S2 are false
    C.
    Both S1 and S2 are true, but S2 is not a reason for S1
    D.
    Both S1 and S2 are true, and S2 is a reason for S1

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  11. The wavelength of a wave with propagation constant (0.1p + j0.4p)m-1 is

  12. A.
    5 m
    B.
    5p m
    C.
    D.
    10 m

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  13. For what positive value of K does the polynomial s4 + 8s3 + 24s2 + 32s + K have roots with zero real parts?

  14. A.
    10
    B.
    20
    C.
    40
    D.
    80

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  15. Which of the following capabilities are available in a Universal Shift Register?

    1. Shift left
    2. Shift right
    3. Parallel load
    4. Serial add
    Select the correct answer from the codes given below:

  16. A.
    2 and 4 only
    B.
    1, 2 and 3
    C.
    1, 2 and 4
    D.
    1, 3 and 4

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