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ECE :: Analog Electronics

  1. It is desired to reduce distortion in an amplifier from 8% to 2% by using 5% negative feedback. The open and closed loop gains respectively are

  2. A.
    60 and 15
    B.
    15 and 60
    C.
    6 and 1.5
    D.
    1.5 and 6

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  3. An ideal op-amp requires

  4. A.
    zero input offset voltage
    B.
    low input offset voltage
    C.
    high input offset voltage
    D.
    infinite input offset voltage

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  5. The JFET in the circuit shown in figure has an IDSS = 10 mA and Vp = -5V. The value of the resistance Rs for a drain current IDS = 6.4 mA is

  6. A.
    156 Ω
    B.
    470 Ω
    C.
    560 Ω
    D.
    1 kΩ

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  7. In figure, V0 =

  8. A.
    zero
    B.
    5.7 V
    C.
    6.9 V
    D.
    12.6 V

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  9. In the op-amp circuit of figure, V0 =

  10. A.
    10 V
    B.
    -10 V
    C.
    5 V
    D.
    -5 V

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  11. In figure the zener has a resistance of 5 ohms. As the load resistance is varied, the output voltage

  12. A.
    will remain constant at 12 V
    B.
    will vary between 12.05 and 12.65 V
    C.
    will vary from 10 to 20 V
    D.
    will remain constant at 12.05 V

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  13. Percentage increase in the reverse saturation current of a diode if the temperature is increased from 25°C to 50°C

  14. A.
    50%
    B.
    500%
    C.
    565.7%
    D.
    575.6%

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  15. The transistor of following figure in Si diode with a base current of 40 μA and ICBO = 0, if VBB = 6V, RE = 2 kΩ and β = 90, IBQ = 20 μA then IEQ =

  16. A.
    1800 μA
    B.
    180 μA
    C.
    2000 μA
    D.
    3000 μA

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  17. In a self bias circuit for CE amplifier, an increase in emitter resistance RE results in

  18. A.
    increase in emitter voltage
    B.
    decrease in emitter voltage
    C.
    increase in emitter current
    D.
    decrease in emitter current

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  19. For a BJT if β = 50, ICEO = 3 μA and IC = 1.2 mA then IE

  20. A.
    1 mA
    B.
    1.2 mA
    C.
    1.3 mA
    D.
    1.4 mA

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