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ECE :: Analog Electronics

Analog Electronics - Section 1
Analog Electronics - Section 2
Analog Electronics - Section 3
Analog Electronics - Section 4
Analog Electronics - Section 5
Analog Electronics - Section 6
Analog Electronics - Section 7
Analog Electronics - Section 8
Analog Electronics - Section 9
Analog Electronics - section-1
Analog Electronics - Section 10
Analog Electronics - Section 11
Analog Electronics - Section 12
Analog Electronics - Section 13
Analog Electronics - Section 14
Analog Electronics - Section 15
Analog Electronics - Section 16
Analog Electronics - Section 17
Analog Electronics - Section 18
Analog Electronics - Section 19
Analog Electronics - Section 20
Analog Electronics - Section 21
Analog Electronics - section-22
Analog Electronics - Section-23

  1. Which of the following contributes to harmonics distortion in amplifiers?

    2. A.
    Positive feedback
    B.
    Presence of noise
    C.
    Defective active device
    D.
    Non-linearity in active device

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  2. Which of the following couplings may cause unwanted clamping?

    3. A.
    Resistive
    B.
    Inductive
    C.
    Capacitive
    D.
    Both (a) or (b)

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  3. The name field effect is related to the __________ layers of a JFET.

    4. A.
    depletion
    B.
    drain
    C.
    source
    D.
    gate

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  4. If input frequency is 50 Hz, the frequency of output wave in a half wave diode rectifier circuit is

    5. A.
    25 Hz
    B.
    50 Hz
    C.
    100 Hz
    D.
    200 Hz

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  5. For an amplifier, the coupling method which gives the highest gain in

    6. A.
    impedance coupling
    B.
    transformer coupling
    C.
    capacitance coupling
    D.
    resistance coupling

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  6. An ideal op-amp can amplify dc signals

    7. A.
    True
    B.
    False

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  7. Consider the following statements :
    The lower cut off frequencies of an RC coupled amplifier depend on

    1. input and output coupling capacitor
    2. emitter by pass capacitors
    3. junction capacitances
    Which of the above are correct?

    8. A.
    1 only
    B.
    2 only
    C.
    1 and 2
    D.
    2 and 3

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  8. Assertion (A): In a circuit using FET, gate is approximately at dc ground

    Reason (R): Self bias stabilizes the quiescent operating point against changes in JFET parameters

    9. A.
    Both A and R are correct and R is correct explanation for A
    B.
    Both A and R are correct but R is not correct explanation for A
    C.
    A is correct R is wrong
    D.
    A is wrong R is correct

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  9. The Darlington pair consists of the following two stages

    10. A.
    CE and CC
    B.
    both CE
    C.
    both CC
    D.
    CE and CB

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  10. Figure represents

    11. A.
    Adder
    B.
    Multiplier
    C.
    Subtractor
    D.
    Log Amplifier

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