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ECE :: Digital Electronics

Digital Electronics - Section 1
Digital Electronics - Section 2
Digital Electronics - Section 3
Digital Electronics - Section 4
Digital Electronics - Section 5
Digital Electronics - Section 6
Digital Electronics - Section 7
Digital Electronics - Section 8
Digital Electronics - Section 9
Digital Electronics - Section 10
Digital Electronics - Section 11
Digital Electronics - Section 12
Digital Electronics - Section 13
Digital Electronics - Section 14
Digital Electronics - Section 15
Digital Electronics - Section 16
Digital Electronics - Section 17
Digital Electronics - Section 18
Digital Electronics - Section 19
Digital Electronics - Section 20
Digital Electronics - Section 21
Digital Electronics - Section 22
Digital Electronics - Section 23
Digital Electronics - Section 24
Digital Electronics - section-25
Digital Electronics - Section-26

  1. In a T flip-flop the output frequency is

    2. A.
    same as input frequency
    B.
    half of I/p frequency
    C.
    double the input frequency
    D.
    none

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  2. The access time of ROM using bipolar transistors is about

    3. A.
    1 sec
    B.
    1 mili sec
    C.
    1 μ sec
    D.
    1 n sec

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  3. In LIFO

    4. A.
    only the top of the stack is immediately accessible
    B.
    only the top of the stack is never accessible
    C.
    only the first-in is accessible
    D.
    only the first-in is not accessible

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  4. 10 in BCD code represent

    5. A.
    10100
    B.
    1100
    C.
    010111
    D.
    None of the above

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  5. In RAM, all the information can be obtained at the output with

    6. A.
    minimum time delay
    B.
    unequal time delay
    C.
    nearly identical time delay
    D.
    maximum time delay

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  6. A 1 ms pulse can be converted into a 10 ms pulse by using which one of the following

    7. A.
    An astable multivibrator
    B.
    Stable multivibrator
    C.
    A bistable multivibrator
    D.
    A J-K flip-flop

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  7. In the DRAM cell in the figure is the Vt of the NMOSFET is 1 V. For the following three combinations of WL and BL voltages.

    8. A.
    5 V, 3 V, 7 V
    B.
    4 V, 3 V, 4 V
    C.
    5 V, 5 V, 5 V
    D.
    4 V, 4 V, 4 V

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  8. Assertion (A): The carry look ahead adder is very fast

    Reason (R): The carry look ahead adder generates the carry and sum digits directly.

    9. A.
    Both A and R are correct and R is correct explanation of A
    B.
    Both A and R are correct but R is not correct explanation of A
    C.
    A is true, R is false
    D.
    A is false, R is true

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  9. The factors which govern fan out of CMOS gates are

    10. A.
    maximum permissible propagation delay
    B.
    input capacitance of each load
    C.
    both (a) and (b)
    D.
    neither (a) nor (b)

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  10. Which of the following subtraction operations do not result in F16?

    1. (BA)16 - (AB)16
    2. (BC)16 - (CB)16
    3. (CB)16 - (BC)16
    4. (CB)16 - (BC)16
    Select the correct answer

    11. A.
    1 and 2
    B.
    1 and 3
    C.
    2 and 3
    D.
    1, 2 and 3

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