ECE :: Digital Electronics
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Assertion (A): Master slave JK flip flop is commonly used in high speed synchronous circuitry
Reason (R): Master slave JK flip flop uses two JK flip flops in cascade.
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Inputs A and B of the given figure are applied to a NAND gate. The output is LOW
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For the NMOS gate in the given figure, F =
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The resolution of 4 bit counting ADC is 0.5 volt, for an Analog input of 6.6 volts. The digital output of ADC will be
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Read the following statements
- The circuitry of ripple counter is more complex than that of synchronous counter.
- The maximum frequency of operation of ripple counter depends on the modulus of the counter.
- The maximum frequency of operation of synchronous counter does not depend on the modulus of the counter.