ECE :: Digital Electronics
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A 4 bit synchronous counter has flip flops having propagation delay of 50 ns each and AND gates having propagation delay of 20 ns each. The maximum frequency of clock pulses can be
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A pulse train with a 1 MHz frequency is counted using a 1024 modulus ripple counter using JK flip flops. The maximum propagation delay for each flip-flop should be
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What will be maximum input that can be converted for a 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000).
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In the given figure shows a logic circuit. The minimum Boolean expression for this circuit is
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If number of information bits is 11, the number of parity bits in Hamming code is
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The number of digit 1 present in the binary representation of 3 x 512 + 7 x 64 + 5 x 8 + 3 is
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= 1 ms = 10 x delay of one flip flop. Therefore delay for one flip-flop = 0.1 ms.
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