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ECE :: Digital Electronics

  1. Typical switching time for ECL is

  2. A.
    5 nano seconds
    B.
    5 micro seconds
    C.
    5 milli seconds
    D.
    5 seconds

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  3. For the K map of the given figure the simplified Boolean expression is

  4. A.
    A B + A B
    B.
    B
    C.
    A
    D.
    AB

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  5. For a logic family
    VOH is the minimum output high level voltage

    1. VOL is the maximum output low level voltage
    2. VIH is the minimum acceptable input high level voltage
    3. VIL is the maximum acceptable input low level voltage
    The correct relationship is

  6. A.
    VIH > V0H > VIL > V0L
    B.
    VOH > VIH > VIL > V0L
    C.
    VIH > VOH > VOL > VIL
    D.
    VOH > VIH > VOL > VIL

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  7. In which function is each term known as minterm?

  8. A.
    SOP
    B.
    POS
    C.
    Hybrid
    D.
    Both SOP and POS

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  9. How many and what are the machine cycles needed for execution of MOV D, C?

  10. A.
    1, Fetch
    B.
    2, Fetch and Memory Read
    C.
    2, Memory Read and Memory write
    D.
    2, Fetch 4 Bus idle

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  11. The output data lines of microprocessor and memories are usually tristated because

  12. A.
    more than one device can transmit information over the data bus by enabling only one device at a time
    B.
    more than one device can transmit information over the data bus at the same time
    C.
    the data lines can be multiplexed for both I/P and O/P
    D.
    it increases the speed of data transfers over the data bus

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  13. In the NMOS inverter

  14. A.
    the driver and active load are enhancement type
    B.
    driver is enhancement type and load depletion type
    C.
    driver is depletion type and load enhancement type
    D.
    both driver and load are depletion type

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  15. A counter displays a sequence of numbers. If a reading corresponds to the hexadecimal number F52E, the next two readings are respectively

  16. A.
    F52F, F520
    B.
    F530, F531
    C.
    F52F, F530
    D.
    F52F, F52G

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